Freescale MC9S12NE64 Hardware design

Freescale MC9S12NE64: "Hardware design.

First you gotta have hardware. Or at least be waiting for a board design to come back from the pcb proto place. Since the choice of development environment didn't impact the hardware, and no evaluation board existed in 2004, the hardware design definitely came first.

The March 2005 issue of Circuit Cellar is a gold mine for this design - if it had arrived in November 2004. Regardless, it has an excellent write-up of the same quirks and niggles I ran across. The article is 'Single-IC 10/100 Ethernet Solution' by Fred Eady, go buy it before starting a design with this chip. In addition, the article on FAT16 for SD/MMC would have been fabulous to have, but prllc.com's FAT12/FAT16 SD library had already been purchased and integrated. More on this in phase 4 below.

Follow application note AN2759. Read it and re-read it. Page 6 is the schematic, showing the 12.4K 1% for Rbias, which is not documented anywhere else. Look over the chip data sheet as well. Note split grounds in the board layout on page 17. I always follow things like this, as far as I'm concerned if Freescale (or any other large company) can be bothered to write it up with diagrams and screen captures it must be important. Besides, 100 megabit ethernet is a lot of fast-moving signals, and taking shortcuts is inviting disaster in the works-sometimes, can't-pin-down-the-problem type of nightmares. Network problems created by software bugs and general configuration mistakes are difficult enough to deal with, it would be really bad if the hardware itself were flaky as well. I followed the guidance in this app note, checked my board layout carefully, and it worked fine.

Major items of note in this design:
0.1uF decoupling caps were added to all those power pins that don't have .22uF as shown in the schematic.
Status LEDs were done by the ethernet hardware, not software. The OpenTCP port can be compiled either way.
Ethernet jack with integrated LEDs and m"